Clock generating circuit, semiconductor device including the same, and data processing system
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United States of America Patent
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Jan 1, 2013
Grant Date -
May 31, 2012
app pub date -
Jan 27, 2012
filing date -
Sep 8, 2009
priority date (Note) -
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Abstract
A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.
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