Memory system for controlling distribution of packet data across a switch

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8345701
SERIAL NO

10921429

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A memory system for ingress processing is arranged to access multiple banks in a time interleaved fashion. Each memory bank has an associated memory bank manager, which is arranged to track the contents and egress ports associated with data stored in the memory bank. Incoming data from ingress traffic is evaluated and segregated based on criteria. One of the memory banks is identified based on the criteria, and the incoming data is stored in the identified memory bank in the next available write cycle timeslot. Data constructs in the memory bank manager are updated to indicate the location and egress port associated with the stored data. The memory bank managers submit egress transmit bids to a master scheduler, which controls access to the memory banks. The memory banks are readout in interleaved fashion such that the effective average traffic arrival rate is increased and memory bandwidth requirements are reduced.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
F5 NETWORKS, INC.SEATTLE, WA325

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Davis, Greg W Liberty Lake, US 13 373
Mimms, Alan B Spokane, US 6 37

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
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ZETTACOM, INC. (1)
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LUCENT TECHNOLOGIES INC. (1)
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CISCO TECHNOLOGY, INC. (1)
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INPHI CORPORATION (1)
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ALCATEL LUCENT (1)
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Network Equipment Technologies, Inc. (1)
* 6424659 Multi-layer switching apparatus and method 207 1998
 
ALTERA CORPORATION (1)
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RAMBUS INC. (1)
* 6603771 Highly scalable architecture for implementing switch fabrics with quality of services 4 1999
 
WSOU INVESTMENTS, LLC (2)
* 6044061 Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch 77 1998
* 6160812 Method and apparatus for supplying requests to a scheduler in an input buffered multiport switch 114 1998
 
PACKET ENGINES INCORPORATED (2)
* 6470021 Computer network switch with parallel access shared memory architecture 8 1998
* 6920146 Switching device with multistage queuing scheme 48 1998
 
NEC CORPORATION (1)
* 6618379 RRGS-round-robin greedy scheduling for input/output terabit switches 50 1998
 
ATI TECHNOLOGIES ULC (1)
* 6789154 Apparatus and method for transmitting data 46 2000
 
RPX CORPORATION (1)
* 6625177 Circuit, method and/or architecture for improving the performance of a serial communication link 1 1999
 
RENESAS ELECTRONICS AMERICA INC. (1)
* 6065092 Independent and cooperative multichannel memory architecture for use with master device 201 1997
 
L-3 COMMUNICATIONS INTEGRATED SYSTEMS L.P. (1)
* 6317415 Method and system for communicating information in a network 23 1998
 
XYLON LLC (1)
* 6144640 ATM switch 13 1997
 
ALCATEL USA SOURCING, L.P. (1)
* 5999518 Distributed telecommunications switching system and method 232 1997
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (2)
* 8750306 Network management module for a vehicle communication network 4 2011
* 2012/0106,549 NETWORK MANAGEMENT MODULE FOR A VEHICLE COMMUNICATION NETWORK 2 2011
* Cited By Examiner

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