Bitline floating circuit for memory power reduction
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United States of America Patent
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Jan 8, 2013
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N/A
app pub date -
Dec 22, 2010
filing date -
Dec 22, 2010
priority date (Note) -
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Abstract
Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.
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