Emulation of power shutoff behavior for integrated circuits

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United States of America Patent

PATENT NO 8352235
SERIAL NO

11966602

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Abstract

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A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beletsky, Platon San Jose, US 6 61
Lin, Tsair-Chin Saratoga, US 13 178
Zhu, Bing Fremont, US 53 530

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