Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system
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United States of America Patent
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Jan 8, 2013
Grant Date -
Dec 2, 2010
app pub date -
May 26, 2009
filing date -
May 26, 2009
priority date (Note) -
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Abstract
Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.
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