Method for fabricating semiconductor devices with reduced junction diffusion
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 15, 2013
Grant Date -
Feb 9, 2012
app pub date -
Oct 19, 2011
filing date -
Sep 27, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully