Resonant clock distribution network architecture for tracking parameter variations in conventional clock distribution networks

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United States of America Patent

PATENT NO 8358163
APP PUB NO 20110084775A1
SERIAL NO

12903188

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Abstract

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A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

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Patent Owner(s)

  • CYCLOS SEMICONDUCTOR, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ishii, Alexander Princeton, US 15 1024
Papaefthymiou, Marios C Ann Arbor, US 23 1736

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