Chip scale package assembly in reconstitution panel process format
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United States of America Patent
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Feb 5, 2013
Grant Date -
Sep 27, 2012
app pub date -
Mar 25, 2011
filing date -
Mar 25, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.
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