Programmable logic device wakeup using a general purpose input/output port
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United States of America Patent
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Feb 5, 2013
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N/A
app pub date -
Mar 1, 2011
filing date -
Mar 1, 2011
priority date (Note) -
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Abstract
In one embodiment, a programmable logic device such as an FPGA includes a programmable fabric adapted to operate normally and in a sleep mode, and a general purpose input/output port (I/O). The I/O port is adapted to function in conventional fashion during normal operation of the programmable fabric and as a wakeup control port during the sleep mode.
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