Testing of soft error detection logic for programmable logic devices

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United States of America Patent

PATENT NO 8370691
SERIAL NO

13299507

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Abstract

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In one embodiment, a programmable logic device (PLD) with configuration memory includes at least one configuration memory cell and soft error detection (SED) logic for checking for errors in data stored by the configuration memory. The SED logic calculates a present data value for the configuration memory for comparison with a pre-calculated data value. A fuse within the PLD is configurable in a first logic state to enable the SED logic to read from the configuration memory cell in calculating the present data value and configurable in a second logic state to prevent the SED logic from reading from the configuration memory cell in calculating the present data value. The SED logic may be tested for correct operation by writing data representing a soft error into the configuration memory cell and enabling the SED logic to read from the configuration memory cell in calculating the present data value.

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Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION5555 NE MOORE CT HILLSBORO OR 97124

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Chan-Chi Jason Fremont, US 14 268
Wei, Qin San Jose, US 12 52
Yew, Ting San Jose, US 13 88

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