CMOS compatible pressure sensor for low pressures
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United States of America Patent
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Feb 26, 2013
Grant Date -
Jun 23, 2011
app pub date -
Dec 17, 2010
filing date -
Dec 21, 2009
priority date (Note) -
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Abstract
Pressure sensors having a topside boss and a cavity formed using deep reactive-ion etching (DRIE) or plasma etching. Since the boss is formed on the topside, the boss is aligned to other features on the topside of the pressure sensor, such as a Wheatstone bridge or other circuit elements. Also, since the boss is formed as part of the diaphragm, the boss has a reduced mass and is less susceptible to the effects of gravity and acceleration. These pressure sensors may also have a cavity formed using a DRIE or plasma etch. Use of these etches result in a cavity having edges that are substantially orthogonal to the diaphragm, such that pressure sensor die area is reduced. The use of these etches also permits the use of p-doped wafers, which are compatible with conventional CMOS technologies.
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