Configuring multiple programmable logic devices with serial peripheral interfaces
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United States of America Patent
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Feb 26, 2013
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N/A
app pub date -
Apr 1, 2010
filing date -
Apr 1, 2010
priority date (Note) -
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Abstract
In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.
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