Semiconductor package having electrical connecting structures and fabrication method thereof
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United States of America Patent
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Mar 5, 2013
Grant Date -
Jun 30, 2011
app pub date -
Aug 19, 2010
filing date -
Dec 25, 2009
priority date (Note) -
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Abstract
A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.
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