Buffer to drive reference voltage
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United States of America Patent
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Mar 5, 2013
Grant Date -
Jul 19, 2012
app pub date -
Jan 14, 2011
filing date -
Jan 14, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
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