Method and apparatus for hardware XML acceleration

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8392824
APP PUB NO 20100180195A1





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A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.

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Inventor Name Address # of filed Patents Total Citations
Behrens, Jochen Santa Cruz, US 8 251
Dignum, Marcelino M Menlo Park, US 15 225
Nag, Biswadeep Fremont, US 9 405
Pericas-Geertsen, Santiago M Palm Beach Gardens, US 3 55
Petry, John P San Diego, US 16 232
Seltzer, Wayne F San Jose, US 7 167
Zaumen, William T Palo Alto, US 10 536

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