Cross-point self-aligned reduced cell size phase change memory
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United States of America Patent
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Mar 12, 2013
Grant Date -
Apr 12, 2012
app pub date -
Oct 6, 2010
filing date -
Oct 6, 2010
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Abstract
A programmable memory array is disclosed in which the phase change memory cells are self-aligned at the access devices and at the cross-points of the bit lines and the word lines. A method for making the array employs one line mask to define the bit lines and another line mask to define the word lines. The front end of line (FEOL) memory cell elements are in the same layer as the polysilicon gates. The bit lines and the word lines intersect over the devices, and the memory cell elements are formed at the intersections of the bit lines and the word line.
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