Memory controller
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United States of America Patent
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Mar 12, 2013
Issued Date -
N/A
app pub date -
May 2, 2012
filing date -
Apr 24, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
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