STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS

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United States of America Patent

SERIAL NO

13440313

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Crisp, Richard Dewitt Hornitos, US 113 2793
Haba, Belgacem Saratoga, US 769 23924
Lambrecht, Frank Mountain View, US 74 1658
Zohni, Wael San Jose, US 153 3070

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