Interconnect structure for integrated circuits
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United States of America Patent
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Mar 26, 2013
Grant Date -
Jan 4, 2007
app pub date -
Jun 29, 2005
filing date -
Jun 29, 2005
priority date (Note) -
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Abstract
The present invention discloses an interconnect structure for an integrated circuit formed on a semiconductor substrate. In one embodiment, the first conductive layer is formed above the semiconductor substrate. A first via contact is formed on the first conductive layer. A second via contact is formed on the first via contact. A second conductive layer is formed on the second via contact. One of the first and second via contacts has a cross-sectional area substantially larger that of another for improving a landing margin thereof, thereby eliminating a need of using a landing pad between the first and second via contacts.
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