Delay locked loop having internal test path
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United States of America Patent
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Mar 26, 2013
Grant Date -
May 11, 2006
app pub date -
Nov 10, 2004
filing date -
Nov 10, 2004
priority date (Note) -
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Abstract
A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.
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