Single-strobe operation of memory devices
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United States of America Patent
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Mar 26, 2013
Grant Date -
Apr 28, 2011
app pub date -
Jan 5, 2011
filing date -
Oct 17, 2007
priority date (Note) -
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Abstract
An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
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