Method for repeated block modification for chip routing
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United States of America Patent
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Mar 26, 2013
Grant Date -
N/A
app pub date -
May 30, 2008
filing date -
Jun 1, 2007
priority date (Note) -
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Abstract
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.
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