Gate trim process using either wet etch or dry etch approach to target CD for selected transistors
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United States of America Patent
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Apr 2, 2013
Grant Date -
Feb 9, 2012
app pub date -
Oct 21, 2011
filing date -
Apr 15, 2009
priority date (Note) -
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Abstract
Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
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