Substrate with embedded patterned capacitance
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United States of America Patent
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Apr 2, 2013
Grant Date -
May 3, 2012
app pub date -
Jan 6, 2012
filing date -
Jul 28, 2008
priority date (Note) -
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Abstract
A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
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