Wide frequency range delay locked loop
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United States of America Patent
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Apr 2, 2013
Issued Date -
N/A
app pub date -
Jun 14, 2012
filing date -
Dec 31, 2002
priority date (Note) -
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Abstract
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
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