Method and device for checking the integrity of a logic signal, in particular a clock signal
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United States of America Patent
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Apr 2, 2013
Grant Date -
Aug 28, 2008
app pub date -
Jan 28, 2008
filing date -
Jan 29, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
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International Classification(s)
- H04L:TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAP....
- H03M:CODING, DECODING OR CODE CONVERSION, IN GENERAL
- G06F:ELECTRIC DIGITAL DATA PROCESSING
- G11B:INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BET....
- G01R:MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC V....
- G06K:RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD ....
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