Importance

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Abstract

Some embodiments of the invention provide an integrated circuit (“IC”) that includes numerous configurable nodes arranged in an array having several rows and columns. In some embodiments, the configurable nodes include a first group of configurable aligned along a particular direction and a second group of configurable nodes aligned along a different direction. The IC also includes a set of direct offset turn connections arranged across the node array in a repetitive nested architecture. Each direct offset turn connection connects a node from the first group of configurable nodes to a node from the second group of configurable nodes. Each direct offset turn connection includes at least two wire segments that are arranged in at least two different directions and intersect to define a turn. No direct offset turn connection overlaps with another direct offset turn connection.

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First Claim