N channel JFET based digital logic gate structure
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United States of America Patent
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Apr 9, 2013
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N/A
app pub date -
May 2, 2011
filing date -
May 2, 2011
priority date (Note) -
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Abstract
An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.
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