Erase and programming techniques to reduce the widening of state distributions in non-volatile memories
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United States of America Patent
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Apr 9, 2013
Grant Date -
Nov 24, 2011
app pub date -
Mar 25, 2011
filing date -
May 21, 2010
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Abstract
Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.
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