System and method of increasing addressable memory space on a memory board
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 9, 2013
Grant Date -
Jan 20, 2011
app pub date -
Jul 16, 2009
filing date -
Jul 16, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully