Associating input/output device requests with memory associated with a logical partition
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United States of America Patent
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Apr 9, 2013
Grant Date -
Dec 29, 2011
app pub date -
Jun 23, 2010
filing date -
Jun 23, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.
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