Master-slave flip-flop circuit
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United States of America Patent
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Apr 16, 2013
Grant Date -
Dec 8, 2011
app pub date -
Jun 1, 2011
filing date -
Jun 3, 2010
priority date (Note) -
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Abstract
A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal.
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