Generating ROM bit cell arrays
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United States of America Patent
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Apr 16, 2013
Grant Date -
Oct 13, 2011
app pub date -
Apr 7, 2011
filing date -
Jan 9, 2009
priority date (Note) -
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Abstract
A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.
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