Memory controller and device with data strobe calibration
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United States of America Patent
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Apr 16, 2013
Grant Date -
Jun 17, 2010
app pub date -
Feb 24, 2010
filing date -
Mar 21, 2006
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.
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