Programmable drive strength in memory signaling
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United States of America Patent
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Apr 16, 2013
Grant Date -
Sep 22, 2011
app pub date -
Mar 19, 2010
filing date -
Mar 19, 2010
priority date (Note) -
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Abstract
Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.
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