Failure analysis apparatus, method
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 16, 2013
Grant Date -
Jul 29, 2010
app pub date -
Jan 28, 2010
filing date -
Jan 29, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully