Integrated circuit with memory built-in self test (MBIST) circuitry having enhanced features and methods
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United States of America Patent
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Apr 16, 2013
Grant Date -
Mar 22, 2012
app pub date -
Sep 16, 2010
filing date -
Sep 16, 2010
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Abstract
Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.
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