System and method for compressed post-OPC data

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United States of America Patent

PATENT NO 8423924
SERIAL NO

13330566

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Abstract

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According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pierrat, Christophe Santa Clara, US 193 6320

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