Memory device with recessed construction between memory constructions
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United States of America
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Apr 23, 2013
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app pub date -
Feb 10, 2011
filing date -
Feb 10, 2011
priority date (Note) -
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Abstract
A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.
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