Semiconductor device having active region and dummy wirings

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8426969
APP PUB NO 20120126360A1
SERIAL NO

13362385

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Abstract

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There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

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Patent Owner(s)

Patent OwnerAddress
ACACIA RESEARCH GROUP LLC767 3RD AVE 6TH FLOOR NEW YORK NY 10017

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kuroda, Kenichi Tachikawa, JP 126 2341
Watanabe, Kozo Kokubunji, JP 87 893
Yamamoto, Hirohiko Hachioji, JP 40 802

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