Sampling phase lock loop (PLL) with low power clock buffer
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United States of America Patent
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Apr 23, 2013
Grant Date -
Feb 14, 2013
app pub date -
Oct 17, 2012
filing date -
Dec 20, 2010
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Abstract
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.
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