Clock state independent retention master-slave flip-flop
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United States of America Patent
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Apr 23, 2013
Grant Date -
Dec 8, 2011
app pub date -
Dec 28, 2010
filing date -
Jun 3, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path 16 or a second path 22, 24, 4, 10 in dependence upon the phase of the clock signal. During both phases of the clock signal the output signal is driven in a well defined state to reflect the signal stored within the retention circuitry. There is thus provided a clock independent retention master-slave flip-flop circuit. Both high density and high speed variants of the flip-flop circuit may use the technique.
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