Device for controlling a power transistor
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United States of America Patent
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Apr 23, 2013
Grant Date -
Jan 13, 2011
app pub date -
Jun 18, 2010
filing date -
Jul 7, 2009
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention relates to a gate control device for a JFET-type transistor that has a gate, a drain and a source. The gate control device includes a voltage generation circuit comprising an output connected to the gate of the transistor, where the circuit is designed to generate at the output a reference gate-source voltage following a predetermined voltage ramp. A voltage limiting circuit is designed to limit the reference gate-source voltage to a predetermined maximum value when the gate-source voltage at the terminals of the JFET transistor has reached said maximum value.
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