Bit scan circuits and method in non-volatile memory

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United States of America Patent

PATENT NO 8427884
APP PUB NO 20120321032A1
SERIAL NO

13164618

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Abstract

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A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES LLC6900 DALLAS PARKWAY SUITE 325 PLANO TX 75024

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chen Mountain View, US 720 3975
Kuo, Tien-chien Sunnyvale, US 42 532
Liu, Bo Milpitas, US 672 3701
Park, Jongmin Cupertino, US 87 647

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