Bit scan circuits and method in non-volatile memory
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United States of America Patent
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Apr 23, 2013
Grant Date -
Dec 20, 2012
app pub date -
Jun 20, 2011
filing date -
Jun 20, 2011
priority date (Note) -
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Abstract
A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate†any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass†to “pass†state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
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