Processor fault tolerance through translation lookaside buffer refresh
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United States of America Patent
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Apr 23, 2013
Grant Date -
N/A
app pub date -
Jun 11, 2009
filing date -
Jun 11, 2009
priority date (Note) -
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Abstract
Techniques are provided herein to provide a processor device that has tolerance for faults associated with operations of a translation lookaside buffer. In a processor device, contents of a translation lookaside buffer are stored in a memory that is protected by an error correction code (ECC) to provide an ECC-protected backup copy of the contents of the translation lookaside buffer. When a miss exception of the translation lookaside buffer is triggered during execution of a processor function, the contents of the translation lookaside buffer is refreshed with the ECC-protected backup copy. Future operations of the processor are made using the refreshed contents of the translation lookaside buffer.
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