Programmable logic systems and methods employing configurable floating point units
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United States of America Patent
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Apr 23, 2013
Grant Date -
Jan 13, 2011
app pub date -
Sep 17, 2010
filing date -
Feb 1, 2006
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Abstract
A programmable system is disclosed having multiple configurable floating point units (“FPUâ€) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.
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