Edge-based decoders for low-density parity-check codes
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United States of America Patent
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Apr 23, 2013
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app pub date -
Dec 12, 2008
filing date -
Dec 12, 2007
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Abstract
Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.
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