Methods and apparatus for error checking code decomposition
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United States of America Patent
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Apr 23, 2013
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N/A
app pub date -
Nov 20, 2009
filing date -
Apr 12, 2006
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Abstract
Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
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