Method of verifying logic circuit including decoders and apparatus for the same
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United States of America Patent
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Apr 23, 2013
Grant Date -
Mar 4, 2010
app pub date -
Aug 25, 2009
filing date -
Aug 26, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
A logic verification apparatus for verifying a logic circuit includes a line recognition unit that recognizes signal lines in the circuit based on design information regarding the circuit as a starting point; a decoder recognition unit that recognizes an area including an AND gate that outputs a certain logical value and an inverter as a decoder circuit area based on the design information, and determines a logical value of an input signal inputted to the recognized decoder circuit area when a logical value of the starting point has a specific logical value; and a determination unit that determines whether a logical configuration of the recognized decoder circuit area is correct based on the number of input signals and a combination of logical values of input signals between the recognized decoder circuit areas.
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