Cache performance prediction, partitioning and scheduling based on cache pressure of threads

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United States of America Patent

PATENT NO 8429665
APP PUB NO 20110231857A1
SERIAL NO

12727705

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Abstract

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A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.

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Patent Owner(s)

Patent OwnerAddress
VMWARE LLC3401 HILLVIEW AVENUE PALO ALTO CA 94304

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Waldspurger, Carl A Palo Alto, US 117 6212
West, Richard Easton, US 26 395
Zaroo, Puneet Santa Clara, US 18 342
Zhang, Xiao Rochester, US 369 1003

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